EPICURE: A partitioning and co-design framework for reconfigurable computing

This paper presents a new design methodology able to bridge the gap between an abstract specification and a heterogeneous reconfigurable architecture. The EPICURE contribution is the result of a joint study on abstraction/refinement methods and a smart reconfigurable architecture within the formal Esterel design tools suite. The original points of this work are: (i) a generic HW/SW interface model, (ii) a specification methodology that handles the control, and includes efficient verification and HW/SW synthesis capabilities, (iii) a method for parallelism exploration based on abstract resources/performance estimation expressed in terms of area/delay tradeoffs, (iv) a HW/SW partitioning approach that refines the specification into explicit HW configurations and the associated SW control. The EPICURE framework shows how a cooperation of complementary methodologies and CAD tools associated with a relevant architecture can signficantly improve the designer productivity, especially in the context of reconfigurable architectures

Méthodologie de partitionnement logiciel/matériel pour plateformes reconfigurables dynamiquement

M. Olivier SENTIEYS Professeur, IRISA, Université Rennes 1 (Rapporteur)M. Lionel TORRES Professeur, LIRMM, Université Montpellier II (Rapporteur)M. Michel AUGUIN Directeur de recherche CNRS, I3S, UNSA (Directeur de thèse)M. Charles ANDRÉ Professeur, I3S, UNSA (Président de jury)M. Yvon TRINQUET Professeur, IRCCyN, Université de Nantes (Examinateur)M. Christian GAMRAT Ingénieur (CEA - LIST) (Invité)M. Philippe KAJFASZ Responsable du laboratoire architectures avancées (THALES) (Invité)Reconfigurable systems (or platforms) integrating one or more processors and a programmable matrix on a single die (ex: Excalibur of Altera, Virtex 4-Fx of Xilinx) are getting a large spread. Furthermore, a whole technological field is emerging now in the dynamic reconfiguration area. The designer faces software (specific or generic) and hardware (fixed or reconfigurable) implementation choices for the different parts of the application. For the next generation systems, the increasing complexity requires the use of computer aided design tools. It is necessary to expand or reconsider the actual design approaches in order to adapt them to the possibilities given by the programmable technology.This thesis proposes an automatic hardware/software method targeting systems mixing software and dynamically reconfigurable hardware with the objective of minimizing the total execution time under maximum hardware resource constraint. It provides a complete flow starting from a system level specification of the application (written in SSM: the graphical formalism of the Esterel synchronous language) until its refinement towards RTL level tools. The method, based on a genetic algorithm, takes into account the reconfigurable architecture specificities by adding to the classical spatial partitioning (or assignment) a temporal partitioning step in order to distribute over time the different configurations successively mapped on the reconfigurable part. The performances are evaluated by a scheduling step taking into account the communication times and those due to configuration switching.On parle de plus en plus de systèmes (ou plateformes) reconfigurables qui intègrent sur un même substrat un ou plusieurs cœurs de processeurs et une matrice programmable (ex: Excalibur d'Altera, Virtex 2-Pro et Virtex 4-Fx de Xilinx). Par ailleurs, tout un champ technologique émerge actuellement dans le domaine de la reconfiguration dynamique. Le concepteur se retrouve face à des choix d'implantations logicielles (spécifiques ou génériques) et matérielles (figées ou reconfigurables) pour les différentes parties de l'application. Pour les prochaines générations de systèmes, la complexité croissante nécessite de faire appel à des méthodes et outils d'aide à la prise de décisions. Il est donc nécessaire d'étendre ou de repenser les approches de conception actuelles afin de les adapter aux possibilités offertes par les technologies reconfigurables.Cette thèse propose une méthode automatique de partitionnement logiciel/matériel qui cible des systèmes mixtes logiciel et matériel reconfigurable dynamiquement et a pour objectif de minimiser le temps d'exécution global sous contrainte de surface maximale. Elle offre un flot complet à partir de la spécification au niveau système de l'application (écrite en SSM : formalisme graphique du langage synchrone Esterel) jusqu'à son raffinement vers les outils de niveau RTL. La méthode, basée sur un algorithme génétique, prend en compte les spécificités de l'architecture reconfigurable en ajoutant au partitionnement spatial (ou affectation) classique une étape de partitionnement temporel afin de distribuer dans le temps les configurations successivement implantées sur le reconfigurable. Les performances sont évaluées par une étape d'ordonnancement qui prend en compte les temps de communication et ceux dus aux changements de configurations

Méthodologie de partitionnement logiciel matériel pour plateformes reconfigurables dynamiquement

NICE-BU Sciences (060882101) / SudocSudocFranceF

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Graphic Rendering Application Profiling on a Shared Memory MPSoC Architecture

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Learning-Based Adaptive Management of QoS and Energy for Mobile Robotic Missions

International audienceMobile robotic systems are normally confronted with the shortage of on-board resources such as computing capabilities and energy, as well as significantly influenced by the dynamics of surrounding environmental conditions. This context requires adaptive decisions at run-time that react to the dynamic and uncertain operational circumstances for guaranteeing the performance requirements while respecting the other constraints. In this paper, we propose a reinforcement learning (RL)-based approach for Quality of Service QoS and energy-aware autonomous robotic mission manager. The mobile robotic mission manager leverages the idea of (RL) by monitoring actively the state of performance and energy consumption of the mission and then selecting the best mapping parameter configuration by evaluating an accumulative reward feedback balancing between QoS and energy. As a case study, we apply this methodology to an autonomous navigation mission. Our simulation results demonstrate the efficiency of the proposed management framework and provide a promising solution for the real mobile robotic systems

Partitioning and CoDesign tools & methodology for Reconfigurable Computing: The EPICURE philosophy

As reconfigurable computing solutions are emerging at the hardware level, there is an obvious need for well adapted design tools. This paper describes a research effort currently in progress that tries to address this problem. The EPICURE framework is a new global methodology based on the cooperation of tools adapted for the design of embedded Hardware/Software reconfigurable solutions. Among the many problems in this field, the EPICURE projects focuses on the following: a/ A specification methodology that helps handling the system control and Hardware reconfiguration. b/ Exploration and estimation tools that address the parallelism and architecture exploration phase. c/ A Hardware/Software partitioning method based on a genetic algorithm which has the capability of handling the delay/area/power consumption trade-off. d/ A dedicated interface model (hardware and software) that abstracts the communication in between a standard processor and a reconfigurable device

A 5500-frames/s 85-GOPS/W 3-D Stacked BSI Vision Chip Based on Parallel In-Focal-Plane Acquisition and Processing

International audienceThis paper presents a 3-D stacked vision chip featuring in-focal-plane read-out tightly coupled with flexible computing architecture for configurable high-speed image analysis. The chip architecture is based on a scalable standalone structure integrating image sensor on the top tier and processing elements (PEs) plus memories in the bottom tier. By using 3-D stacking partitioning, our prototype benefits from backside illuminated pixels sensitivity, a fully parallel communication between image sensor and PEs for low-latency performances, while leaving enough room in the bottom tier to embed advanced computing features. One scalable structure embeds a 16x16 pixel array (or 64 x 64 pixels in high-resolution mode), associated with an 8-bit single instruction multiple data (SIMD) processor; fabricated in dual 130-nm 1P6M CMOS process. This paper exhibits a 5500 frames/s and 85 giga operations per second (GOPS)/W in low-resolution mode, with large kernels capabilities through eight directions interpixel communication. Multiflow capability is also demonstrated to execute different programs in different areas of the vision chip